HYBRID EVENT: You can participate in person at Baltimore, Maryland, USA or Virtually from your home or work.
Jyi Tsong Lin, Speaker at Materials Science Conferences
National Sun Yat-Sen University, Taiwan
Title : Can a simple iTFET become a mainstream of future technology generation

Abstract:

In this presentation, we embark on a journey to explore the transformative potential of a simple yet innovative inductive Tunnel Field-Effect Transistor (iTFET), contemplating its possible ascent to a leading role in shaping future technology landscapes. The narrative traverses the realms of simplicity, cost-efficiency, power frugality, multifunctionality, streamlined fabrication, production scalability, and its distinctive attributes. As we set the stage, it is imperative to address the inherent limitations of conventional Gated PIN TFETs. These devices grapple with the vexing issues of gate-bias dependent subthreshold swing (SS) degradation, anemic current drive, substantial leakage current, ambipolar complexities, and the formidable challenge of Trap Assisted Tunneling (TAT). The iTFET, poised as a novel protagonist in this tale, emerges as a harbinger of novel solutions to circumvent these prevailing obstacles. The iTFET's relevance assumes paramount importance when viewed against the backdrop of mainstream CMOS technology's limitations. The industry's pursuit of achieving a subthreshold swing below thermal constraints faces substantial impediments, particularly in applications necessitating ultra-low-power paradigms, such as high-performance yet power-savvy IoT and AI systems. While Tunnel Field-Effect Transistors (TFETs) have tantalized with their promise, their adoption trajectory encounters formidable challenges rooted in manufacturing intricacies, the quest for performance augmentation, and the unwavering quest for reliability.
At the heart of our exploration lies the conundrum of Trap Assisted Tunneling (TAT), a thorn in the side of TFET feasibility. TAT's adverse impact compounds the already challenging endeavor of achieving subthreshold swings smaller than the elusive 60mV threshold. This pivotal challenge reverberates across the industry, influencing transistor switching efficiency and practical real-world implementation. It is precisely this challenge that we aim to dissect and potentially overcome during our discourse. The iTFET, our central protagonist, shines as a beacon of hope and ingenuity. It heralds a paradigm shift in semiconductor device architecture. Unlike conventional MOSFETs, which operate predominantly as majority carrier Gated NPN or PNP devices, TFETs, including iTFET, function as minority carrier tunneling Gated PIN diodes but in a reverse-biased configuration. This departure from convention opens vistas of opportunity for enhanced performance and resilience. Remarkably, the fabrication processes for the iTFET are fully compatible with those of recent CMOS technologies, ensuring seamless integration into contemporary semiconductor manufacturing landscapes. Adding to its allure, the iTFET flaunts an impressively facile fabrication process. Its manufacturing journey is marked by simplicity, efficiency, and a significantly reduced wafer footprint. Notably, its current drive is not tethered to the conventional W/L ratio but is instead directly proportional to the product of channel length (L) and width (W), a distinctive attribute that sets it apart from its predecessors. In summary, this presentation endeavors to illuminate the transformative potential of iTFET technology. It does not merely rest on the promise of overcoming current semiconductor device shortcomings but holds the potential to redefine the very foundations of mainstream technology generation. The iTFET's attributes of simplicity, cost-effectiveness, power efficiency, multifunctionality, ease of fabrication, and scalability, combined with its unique current drive characteristics, make it a compelling candidate for shaping the future of semiconductor technology.

Audience Take Away:

1.    Understanding iTFET Technology: The presentation provides a comprehensive understanding of iTFET technology, including its unique operational principles, characteristics, and advantages.
•    Use: Attendees will be equipped with knowledge about an emerging semiconductor technology, enabling exploration of its potential applications in their work.
•    Benefit: This knowledge can help researchers, engineers, and designers stay at the forefront of semiconductor advancements and consider iTFETs as a viable option in their projects.
2.    Overcoming Conventional Limitations: The presentation highlights how iTFETs address the limitations of conventional TFETs, such as subthreshold swing, current drive, and manufacturing complexity.
•    Use: Attendees can apply these insights to their own research or design projects to potentially overcome similar limitations and enhance device performance.
•    Benefit: This research provides a practical solution to challenges in semiconductor device design, simplifying the job of device designers and improving the efficiency of their work.
3.    Integration into CMOS Technologies: The presentation emphasizes the compatibility of iTFET fabrication processes with recent CMOS technologies.
•    Use: This information is valuable for semiconductor manufacturers and researchers aiming to integrate iTFETs into existing CMOS processes.
•    Benefit: It simplifies the integration process, reducing the effort and cost required for incorporating iTFETs into mainstream semiconductor production, which can ultimately lead to cost-effective and efficient designs.
4.    Performance Enhancement: The presentation discusses how iTFETs offer unique performance characteristics, including simplified current drive calculations.
•    Use: Designers can utilize this knowledge to optimize designs for improved efficiency and performance.
•    Benefit: It can lead to more accurate designs, enhanced device performance, and energy- efficient solutions, benefiting a wide range of applications from IoT devices to high- performance computing.
5.    Future Technology Landscape: The presentation explores the potential of iTFETs in shaping the future technology landscape.
•    Use: Researchers and educators can incorporate this information into work, guiding students and colleagues in exploring emerging semiconductor technologies.
•    Benefit: It expands the body of knowledge in semiconductor research and opens new avenues for innovation, potentially impacting various industries and applications.

Biography:

Jyi-Tsong Lin, a senior member of IEEE. He earned his B.S. degree in physics from National Taiwan Normal University in 1982, his M.S. degree in electronics from National Chiao Tung University in 1984, and his Ph.D. degree in electronics and computer science from the University of Southampton, England in 1993. Since 1984, he has been associated with National Sun Yat-Sen University in Taiwan, where he currently serves as a Professor in the Department of Electrical Engineering. His research focuses on the design and modeling of small-geometry SOI devices, high-speed and low-power circuits of bulk SOI MOSFETs and TFETs, and cutting-edge developments in various semiconductor applications, including solar cells, 1T DRAMs, TFETs and TFT nano devices.

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