Muhammad Ullah

Title : Carbon nanotubes (CNTs) chirality on semiconductor device modeling

Abstract:

To meet the speed, complexity, circuit density, power consumption, and ultimately cost requirements of many advanced applications, scientists have spent decades shrinking device feature sizes for better performance of metal-oxide semiconductor (MOS) technology. However, there are several disadvantages to switching to these nano size MOS devices. Most of the functional failure in nano-scale devices is caused by aging related phenomena such as negative bias temperature instability (NBTI), hot carrier degradation (HCD), and time dependent dielectric breakdown (TDDB). In addition, Silicon devices’ dimensions and material capabilities are beginning to hit their limitations. Scientists and researchers are constantly trying to figure out how to replace the current silicon material with an emerging novel material like carbon nano tube. The goal of this research was to develop a drain current and threshold voltage model for carbon nanotube field effect transistors (CNTFETs) that can be used in the analysis and design of reliable integrated circuits, focusing on the reliability issues of conventional metal oxide semiconductor field-effect transistors (MOSFETs) at the nanoscale. To develop this model, we investigated the atomic structure of carbon nanotubes and used the fundamentals of electrostatics to describe a field-effect transistor. By analysing and defining the electronic structure of carbon nanotubes, we first arrived at analytical formulas for the carrier concentration in carbon nanotubes for various chiral vectors (n, m). By combining several chiral vectors, it is possible to determine the threshold voltage expression that is obtained throughout the procedure as well as the I-V characteristics for CNTFETs. The diameter and chiral angle of carbon nanotubes were shown to be significant determinants of the I-V characteristics and threshold voltage. In terms of the threshold voltage change CNTFET shows better performance 24% less than the conventional MOSFET in 45nm technology node.

Audience Take Away Notes:

• Progress, challenge, and opportunities at semiconductor device field
• Help the audience to understand process and parameter that considered as device level engineer at semiconductor industry
• This research could help other faculty to expand their research and/or teaching
• The threshold voltage change in CNTFET shows better performance than the conventional MOSFET in 45nm technology node

Biography:

Dr. Muhammad Ullah is currently working as an associate professor of electrical and computer engineering at Florida Polytechnic University. His research focuses are the modeling of RLC interconnects in high density integrated circuits and energy-efficient electronic devices (TFET) for logic applications based on emerging 2-D nanomaterials (MoS2, Graphene, and CNT). Before joining Florida Poly, Ullah worked as a full-time lecturer from 2008 to 2011 at the Chittagong University of Engineering & Technology (CUET), Bangladesh. He has taught undergraduate courses in electrical circuits, digital logic designs, signals and systems, and graduate courses in advanced digital signal processing, introduction to VLSI designs, advanced VLSI designs, and emerging nanotechnology, including hands-on experience in MATLAB, Cadence Virtuoso, and HSPICE. In addition, Dr. Ullah has served as a regular reviewer of many journals and conferences, including IEEE TVLSI, IEEE TMI, Microelectronics Journal-Elsevier and Circuits, Systems and Signal Processing-Springer, and ASP Journal of Low Power Electronics.